1. Field of the Invention
The present invention relates to a capacitor formed over a semiconductor substrate and more particularly, to a capacitor with a high dielectric-constant capacitor dielectric and a thick capacitor electrode or electrodes, which is preferably applied to Gigabit-level Dynamic Random-Access Memories (DRAMs).
2. Description of the Related Art
In recent years, the integration level of the semiconductor integrated circuits (TCs) such as DRAMs has been becoming higher and higher and consequently, electronic elements in the ICs have been becoming miniaturized more and more.
Each storage capacitor of a DRAM needs to have a capacitance of approximately 30 fF to realize its information storing function even if the integration scale of the ICs becomes very high and the size of the storage capacitors becomes very small. To cope with this need, conventionally, the thickness increase of a lower electrode to utilize side faces of the lower electrode or the thickness decrease of a capacitor dielectric have been studied and developed.
As a capacitor dielectric for ICs, silicon dioxide (SiO.sub.2) or silicon nitride (Si.sub.3 N.sub.4), each of which has a low dielectric constant of approximately 3 to 7, has been popularly used. The dielectric constant of these two materials is insufficient for Gigabit-level DRAMs. Therefore, to realize Gigabit-level DRAMs, the lower electrode needs to have a large thickness of 5000 .ANG. or more and at the same time, the capacitor dielectric needs to have a small thickness equivalent to several atomic layers.
However, the thickness increase of the lower electrode and the thickness decrease of the capacitor dielectric will cause the following problems.
Specifically, If the lower electrode is formed to have a large thickness of 5000 .ANG. or more, it is very difficult to control the thickness and geometry of the lower electrode within a satisfactory accuracy because of disadvantages occurring in the exposure and dry etching processes. Also, if the capacitor dielectric is formed to have a small thickness equivalent to several atomic layers, electrons tend to penetrate through the capacitor dielectric due to the tunneling phenomenon. This means that the capacitor dielectric loses its function.
Thus, there is a limit to implement the Gigabit-level DRAMs by using SiO.sub.2 or Si.sub.3 N.sub.4 as the capacitor dielectric through the thickness increase technique of the lower electrode and the thickness decrease technique of the capacitor dielectric.
When a high-dielectric-constant material, which has a dielectric constant greater than SiO.sub.2 or Si.sub.3 N.sub.4, is used for the capacitor dielectric, an obtainable capacitance is higher than the case where SiO.sub.2 or Si.sub.3 N.sub.4 is used as the capacitor dielectric. As the high-dielectric-constant material whose dielectric constant is several tens or several hundreds times as much as that of SiO.sub.2 and Si.sub.3 N.sub.4, typically, SrTiO.sub.3, (Ba,Sr)TiO.sub.3 (i.e., BST), and Pb(Zr,Ti) (i.e., PZT) may be used. For example, a capacitor structure of this type for a 256-Megabit DRAM using BST was reported In an article, International Electron Devices Meeting (IEDM), Digest of Technical Papers, 1991, pp. 823-826, which was written by K. Koyama et al.
However, even if a high-dielectric-constant material with a dielectric constant of approximately 300 is used for the capacitor dielectric, a satisfactory capacitance for Glgabit-level DRAMs is unable to be realized.
Thus, in recent years, the thickness increase of a lower electrode in addition to the use of a high-dielectric-constant capacitor dielectric has been studied. For example, a capacitor structure of this type for a Gigabit-level DRAM was reported in an article, IEDM Digest of Technical Papers, 1994, pp. 831-834, which was written by P-Y. Lesaicherre et al. In the capacitor disclosed in this article a capacitor dielectric is made of SrTiO.sub.3 with a high dielectric-constant, and a lower electrode of a storage capacitor has a composite structure formed by a thin TiN layer and a conductive, thick RuO.sub.2 layer. The TiN layer Serves as a barrier to silicon diffused from a polysilicon contact plug, and the RuO.sub.2 layer serves as a barrier to oxygen diffused from an ambient atmosphere.
FIG. 1 shows the configuration of a conventional storage capacitor of this type.
In FIG. 1, an interlayer insulating layer 1102 is formed on a main surface of a single-crystal silicon substrate 1101. A conductive contact plug 1103 is formed in a contact hole of the interlayer insulating layer 1102. The bottom of the plug 1103 is contacted with and electrically connected to the main surface of the substrate 1101.
A thick lower electrode 1104 is formed on the interlayer insulating layer 1102 to be overlapped with the contact plug 1103. The bottom of the lower electrode 1104 is contacted with and electrically connected to the top of the contact plug 1103.
A high dielectric-constant capacitor dielectric layer 1106 is formed on the interlayer insulating layer 1102 to cover the lower electrode 104. The dielectric layer 1106 is contacted with the top and side faces of the thick lower electrode 1104 and the surface of the interlayer insulating layer 1102.
An upper electrode 1107 is formed on the capacitor dielectric layer 1106 to be contacted therewith.
The upper and lower electrodes 1107 and 1104 and the capacitor dielectric layer 1106 constitute the storage capacitor of a DRAM.
With the conventional storage capacitor shown in FIG. 1, the following problems occurring in the process of forming or depositing the high dielectric-constant capacitor dielectric layer 1106 to cover the thick lower electrode 1104 need to be solved.
(i) The high dielectric-constant capacitor dielectric layer 1106 tends to be applied with a large stress near the root or heel 1108 of the thick lower electrode 1104. This is due to the different growing directions of crystal grains of the dielectric layer 1106 near the root 1108.
(ii) At the top corners between the top and side faces of the lower electrode 1104, a seam defect 1201 tends to occur in the capacitor dielectric layer 1106. The seam defect is formed by a lot of sub-defects collected into the narrow region of the capacitor dielectric layer 1106 due to separation and collision of growing columnar crystal grains of the dielectric layer 1106.
(iii) When the lower electrode 1104 is comprised of RU.sub.2 O, the lower electrode 1104 tends to be vaporized or oxidized during the process of forming the high dielectric-constant capacitor dielectric layer 1106 in a high-temperature oxygen atmosphere, resulting In the rough or uneven side faces 1202 of the lower electrode 1104. In this case, the thickness of the capacitor dielectric layer 1106 tends to be decreased locally and the seam defect tends to occur over the rough or uneven side faces 1202 of the lower electrode 1104.
The crack and seam defects in (i), (ii), and (iii) form a leakage path to thereby increase the leakage current between the lower and upper electrodes 1104 and 1107.
On the other hand, when the lower electrode 1104 has a TIN/RuO.sub.2 composite structure shown in the above-described article, 1994 IEDM Digest of Technical Papers, the TiN barrier layer prevents the silicon atoms contained in the polysilicon contact plug 1103 from diffusing Into the lower electrode 1104. The purpose of this TiN/RuO.sub.2 composite structure Is as follows:
If silicon atoms are diffused into the lower electrode 1104 from the polysilicon contact plug 1103, they create silicide. This suicide thus created is then oxidized to be silicon dioxide (SiO.sub.2) during the process of forming the capacitor dielectric layer 1106 in a high-temperature oxygen atmosphere. This means that the SiO.sub.2 layer is serially connected to the high dielectric-constant capacitor dielectric layer 1106. This SiO.sub.2 layer reduces drastically the capacitance of the storage capacitor.
Moreover, TiN tends to be oxidized during the process of depositing the capacitor dielectric layer 1106. Thus, there is a possibility that the contact resistance of the lower electrode 1104 with the contact plug 1103 is increased due to the oxidized TiN.
FIG. 2 shows the configuration of another conventional storage capacitor of this type, which includes an improvement to decrease the leakage current between the lower and upper electrodes. This capacitor is disclosed in the Japanese Non-Examined Patent Publication No. 6-268156 published in 1994.
In FIG. 2, for the sake of simplification of description, the same reference numerals are attached to the same or corresponding elements as those in FIG. 1.
With the improved, conventional storage capacitor shown in FIG. 2, unlike the capacitor shown in FIG. 1, a part 1102a of the interlayer insulating layer 1102 located just below the lower electrode 1104 around the contact plug 1103 is formed to be thicker than the remainder of the layer 1102. In this case, the upper electrode 1107 is not contacted with the lower electrode 1104 due to existence of the part 1102a even if the seam and/or crack defects occur at the corner region 1109 of the dielectric layer 106. This structure decreases the leakage current between the lower and upper electrodes 1104 and 1107.
However, with the conventional storage capacitor shown in FIG. 2, as the deposition method of forming the capacitor dielectric layer 1106, a Physical Vapor Deposition (PVD) process that tends to generate the seam and/or crack defects is used. Therefore, the leakage current decrease is not satisfactory in spite of the existence of the part 1102a.
Also, no consideration is made for the leakage current near the top corners of the lower electrode 1104 and on the side faces thereof.